module phy_no_data_in(
		input	wire	sclk,
		input	wire	resetb,
		
		input	wire	gp0_rxdv_o,
		input	wire	gp1_rxdv_o,
		
		output	wire	phy_no_data_index0,
		output	wire	phy_no_data_index1
		
		);
		

reg	[17:0]	count0,count1;
reg	[2:0]	gp0_rxdv_o_r,gp1_rxdv_o_r;

	

//assign	phy_no_data_index=count0[17] | count1[17];
assign	phy_no_data_index0=count0[17];
assign	phy_no_data_index1=count1[17];

always@(posedge sclk)
	gp0_rxdv_o_r<={gp0_rxdv_o_r[1:0],gp0_rxdv_o};
	
always@(posedge sclk)
	gp1_rxdv_o_r<={gp1_rxdv_o_r[1:0],gp1_rxdv_o};	



always@(posedge sclk or negedge resetb)
	if(!resetb)
		count0<=0;
	else if(gp0_rxdv_o_r[2:1]==2'b01)
		count0<=0;
	else if(count0[17]==0)
		count0<=count0+1'b1;
		
		
always@(posedge sclk or negedge resetb)
	if(!resetb)
		count1<=0;
	else if(gp1_rxdv_o_r[2:1]==2'b01)
		count1<=0;
	else if(count1[17]==0)
		count1<=count1+1'b1;	
		
		
		
endmodule	
